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» Fast Inductance Extraction of Large VLSI Circuits
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ICCAD
2000
IEEE
88views Hardware» more  ICCAD 2000»
13 years 12 months ago
Hierarchical Interconnect Circuit Models
The increasing size of integrated systems combined with deep submicron physical modeling details creates an explosion in RLC interconnect modeling complexity of unmanageable propo...
Michael W. Beattie, Satrajit Gupta, Lawrence T. Pi...
ARCS
2006
Springer
13 years 11 months ago
Biologically-Inspired Optimization of Circuit Performance and Leakage: A Comparative Study
State-of-the-art technologies in very large scale integration (VLSI) allow for the realization of gates with varying energy consumptions and hence delays (i.e., processing speeds) ...
Ralf Salomon, Frank Sill
VLSID
2005
IEEE
224views VLSI» more  VLSID 2005»
14 years 7 months ago
Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits
An accurate and efficient stacking effect macro-model for leakage power in sub-100nm circuits is presented in this paper. Leakage power, including subthreshold leakage power and ga...
Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan,...
GLVLSI
2009
IEEE
143views VLSI» more  GLVLSI 2009»
13 years 11 months ago
Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO
In this paper, we present the design of a P4 (Power-PerformanceProcess-Parasitic) aware voltage controlled oscillator (VCO) at nanoCMOS technologies. Through simulations, we have ...
Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos
ICCD
2000
IEEE
79views Hardware» more  ICCD 2000»
14 years 4 months ago
Efficient Logic Optimization Using Regularity Extraction
This paper presents a new method to extract functionally equivalent structures from logic netlists. It uses a fast functional regularity extraction algorithm based on structural e...
Thomas Kutzschebauch