19 search results - page 3 / 4 » Fast Instruction Cache Simulation Strategies in a Hardware S... |
ICS
2007
Tsinghua U.
14 years 2 months ago
2007
Tsinghua U.
Software or hardware data cache prefetching is an efficient way to hide cache miss latency. However effectiveness of the issued prefetches have to be monitored in order to maximi...
EUROPAR
1999
Springer
14 years 6 days ago
1999
Springer
Processor cycle time continues to decrease faster than main memory access times, placing higher demands on cache memory hierarchy performance. To meet these demands, conventional ...
MICRO
2003
IEEE
14 years 1 months ago
2003
IEEE
A virtual instruction set architecture (V-ISA) implemented via a processor-specific software translation layer can provide great flexibility to processor designers. Recent examp...
22
Voted
CGO
2007
IEEE
14 years 2 months ago
2007
IEEE
Modern memory systems play a critical role in the performance of applications, but a detailed understanding of the application behavior in the memory system is not trivial to atta...
ISPASS
2010
IEEE
14 years 2 months ago
2010
IEEE
—The ongoing move to chip multiprocessors (CMPs) permits greater sharing of last-level cache by processor cores but this sharing aggravates the cache contention problem, potentia...