Abstract. In this paper we outline a procedure to determine appropriate partitioning of programmable logic and interconnect area to minimize overall device area across a broad rang...
We present the structure of an analog integrated circuit design laboratory to instruct at both, senior undergraduate and entry graduate levels. The teaching material includes: a l...
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
We investigate the differences in speed between applicationspecific integrated circuits and custom integrated circuits when each are implemented in the same process technology, wi...
Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the e...