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FPL
2000
Springer
124views Hardware» more  FPL 2000»
13 years 11 months ago
Balancing Logic Utilization and Area Efficiency in FPGAs
Abstract. In this paper we outline a procedure to determine appropriate partitioning of programmable logic and interconnect area to minimize overall device area across a broad rang...
Russell Tessier, Heather Giza
MSE
2003
IEEE
89views Hardware» more  MSE 2003»
14 years 20 days ago
An Analog Integrated Circuit Design Laboratory
We present the structure of an analog integrated circuit design laboratory to instruct at both, senior undergraduate and entry graduate levels. The teaching material includes: a l...
Antonio F. Mondragón-Torres, Terry Mayhugh ...
FPGA
2007
ACM
142views FPGA» more  FPGA 2007»
14 years 1 months ago
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
N. Pete Sedcole, Peter Y. K. Cheung
DAC
2000
ACM
14 years 8 months ago
Closing the gap between ASIC and custom: an ASIC perspective
We investigate the differences in speed between applicationspecific integrated circuits and custom integrated circuits when each are implemented in the same process technology, wi...
David G. Chinnery, Kurt Keutzer
FPGA
2007
ACM
153views FPGA» more  FPGA 2007»
14 years 1 months ago
Variation-aware routing for FPGAs
Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the e...
Satish Sivaswamy, Kia Bazargan