Sciweavers

244 search results - page 46 / 49
» Fast Set Intersection in Memory
Sort
View
ISCAS
2007
IEEE
92views Hardware» more  ISCAS 2007»
14 years 2 months ago
Macroblock-Level Adaptive Scan Scheme for Discrete Cosine Transform Coefficients
—Discrete Cosine Transform (DCT) has been widely used in image/video coding systems, where zigzag scan is usually employed for DCT coefficient organization. However, due to local...
Li Zhang, Wen Gao, Qiang Wang, Debin Zhao
ICASSP
2011
IEEE
12 years 11 months ago
Online Kernel SVM for real-time fMRI brain state prediction
The Support Vector Machine (SVM) methodology is an effective, supervised, machine learning method that gives stateof-the-art performance for brain state classification from funct...
Yongxin Taylor Xi, Hao Xu, Ray Lee, Peter J. Ramad...
IEEEPACT
2007
IEEE
14 years 2 months ago
A Flexible Heterogeneous Multi-Core Architecture
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
Miquel Pericàs, Adrián Cristal, Fran...
ICS
2011
Tsinghua U.
12 years 11 months ago
Hystor: making the best use of solid state drives in high performance storage systems
With the fast technical improvement, flash memory based Solid State Drives (SSDs) are becoming an important part of the computer storage hierarchy to significantly improve perfo...
Feng Chen, David A. Koufaty, Xiaodong Zhang
ASPLOS
2009
ACM
14 years 8 months ago
Phantom-BTB: a virtualized branch target buffer design
Modern processors use branch target buffers (BTBs) to predict the target address of branches such that they can fetch ahead in the instruction stream increasing concurrency and pe...
Ioana Burcea, Andreas Moshovos