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ASPDAC
2006
ACM
95views Hardware» more  ASPDAC 2006»
14 years 1 months ago
A fast logic simulator using a look up table cascade emulator
— This paper shows a new type of a cycle-based logic simulation method using a Look-Up Table (LUT) cascade emulator. The method first transforms a given circuit into LUT cascade...
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
DAC
1999
ACM
13 years 11 months ago
Using Lower Bounds During Dynamic BDD Minimization
Ordered Binary Decision Diagrams BDDs are a data structure for representation and manipulation of Boolean functions often applied in VLSI CAD. The choice of the variable orderin...
Rolf Drechsler, Wolfgang Günther
ASPDAC
2004
ACM
118views Hardware» more  ASPDAC 2004»
14 years 24 days ago
Minimization of memory size for heterogeneous MDDs
Abstract— In this paper, we propose exact and heuristic algorithms for minimizing the memory size for heterogeneous Multivalued Decision Diagrams (MDDs). In a heterogeneous MDD, ...
Shinobu Nagayama, Tsutomu Sasao
CORR
2008
Springer
142views Education» more  CORR 2008»
13 years 7 months ago
Declarative Combinatorics: Boolean Functions, Circuit Synthesis and BDDs in Haskell
We describe Haskell implementations of interesting combinatorial generation algorithms with focus on boolean functions and logic circuit representations. First, a complete exact c...
Paul Tarau
DAC
1997
ACM
13 years 11 months ago
Safe BDD Minimization Using Don't Cares
In many computer-aided design tools, binary decision diagrams (BDDs) are used to represent Boolean functions. To increase the efficiency and capability of these tools, many algor...
Youpyo Hong, Peter A. Beerel, Jerry R. Burch, Kenn...