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DATE
2003
IEEE
91views Hardware» more  DATE 2003»
14 years 1 months ago
Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs
In system-level platform-based embedded systems design, the mapping model is a crucial link between the application model and the architecture model. All three models must match w...
Vladimir D. Zivkovic, Erwin A. de Kock, Pieter van...
DAC
2008
ACM
14 years 9 months ago
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Current source based cell models are becoming a necessity for accurate timing and noise analysis at 65nm and below. Voltage waveform shapes are increasingly more difficult to repr...
S. Raja, F. Varadi, Murat R. Becer, Joao Geada
DATE
2009
IEEE
126views Hardware» more  DATE 2009»
14 years 3 months ago
Fast and accurate protocol specific bus modeling using TLM 2.0
—The need to have Transaction Level models early in the design cycle is becoming more and more important to shorten the development times of complex Systems-on-Chip (SoC). These ...
H. W. M. van Moll, Henk Corporaal, Víctor R...
NOCS
2007
IEEE
14 years 2 months ago
Fast, Accurate and Detailed NoC Simulations
Network-on-Chip (NoC) architectures have a wide variety of parameters that can be adapted to the designer’s requirements. Fast exploration of this parameter space is only possib...
Pascal T. Wolkotte, Philip K. F. Hölzenspies,...
VLSID
2005
IEEE
100views VLSI» more  VLSID 2005»
14 years 8 months ago
A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model
Buffer insertion method plays a great role in modern VLSI design. Many buffer insertion algorithms have been proposed in recent years. However, most of them used simplified delay ...
Yibo Wang, Yici Cai, Xianlong Hong