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» Fast simulation of VLSI interconnects
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ISCAS
2007
IEEE
202views Hardware» more  ISCAS 2007»
14 years 1 months ago
A VLSI Architecture for a Fast Computation of the 2-D Discrete Wavelet Transform
In this paper, an efficient VLSI architecture for a fast computation of the 2-D discrete wavelet transform (DWT) is proposed. The architecture employing a three-stage cascade in p...
Chengjun Zhang, Chunyan Wang, M. Omair Ahmad
SIGMETRICS
1995
ACM
13 years 10 months ago
Talisman: Fast and Accurate Multicomputer Simulation
Talisman is a simulator that models the execution semantics and timing of a multicomputer. Talisman is unique in combining high semantic accuracy, high timing accuracy, portabilit...
Robert C. Bedichek
ICCAD
1994
IEEE
115views Hardware» more  ICCAD 1994»
13 years 11 months ago
Fast transient power and noise estimation for VLSI circuits
Abstract - Today's digital design systems are running out of steam, when it comes to meeting the challenges presented by simultaneous switching, power consumption and reliabil...
Wolfgang T. Eisenmann, Helmut E. Graeb
ISCAS
2008
IEEE
144views Hardware» more  ISCAS 2008»
14 years 1 months ago
A novel VLSI iterative divider architecture for fast quotient generation
—In this paper, a novel VLSI iterative divider architecture for fast quotient generation that is based on radix-2 non-restoring division is proposed. To speed up the quotient gen...
Tso-Bing Juang, Sheng-Hung Chen, Shin-Mao Li
VLSID
2005
IEEE
100views VLSI» more  VLSID 2005»
14 years 7 months ago
A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model
Buffer insertion method plays a great role in modern VLSI design. Many buffer insertion algorithms have been proposed in recent years. However, most of them used simplified delay ...
Yibo Wang, Yici Cai, Xianlong Hong