Fast transient power and noise estimation for VLSI circuits

Abstract - Today's digital design systems are running out of steam, when it comes to meeting the challenges presented by simultaneous switching, power consumption and reliability constraints emerging in VLSI circuits. In this paper a new technique to accurately estimate the transient behavior of large CMOS cell-based circuits in a reasonable amount of time is presented. Gate-level simulation and a consistent modeling methodology are employed to compute the time-domain waveforms for signal voltages, supply currents, power consumption and 1I noise on power lines. This can be done for circuit blocks and complete designs by our new tool POWTIM, which adds SPICE-like capabilities to digital design systems.

• Type: Conference
• Year: 1994
• Where: ICCAD
• Authors: Wolfgang T. Eisenmann, Helmut E. Graeb
• Keywords: CMOS Cell-based Circuits, Digital Design Systems, Hardware, ICCAD 1994, Power Consumption