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» FastRoute: a step to integrate global routing into placement
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ISPD
2009
ACM
79views Hardware» more  ISPD 2009»
14 years 2 months ago
A routing approach to reduce glitches in low power FPGAs
Glitches (spurious transitions) are common in electronic circuits. In this paper we present a novel approach to reduce dynamic power in FPGAs by reducing glitches during the routi...
Quang Dinh, Deming Chen, Martin D. F. Wong
DATE
2003
IEEE
84views Hardware» more  DATE 2003»
14 years 27 days ago
Interconnect Planning with Local Area Constrained Retiming
We present a framework that considers global routing, repeater insertion, and flip-flop relocation for early interconnect planning. We formulate the interconnect retiming and ï¬...
Ruibing Lu, Cheng-Kok Koh
SLIP
2005
ACM
14 years 1 months ago
Congestion prediction in early stages
Routability optimization has become a major concern in the physical design cycle of VLSI circuits. Due to the recent advances in VLSI technology, interconnect has become a dominan...
Chiu-Wing Sham, Evangeline F. Y. Young
GLVLSI
2000
IEEE
145views VLSI» more  GLVLSI 2000»
14 years 8 hour ago
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...
Cheng-Kok Koh, Patrick H. Madden
DAC
2007
ACM
14 years 8 months ago
An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design
The flip-chip package provides a high chip-density solution to the demand for more I/O pads of VLSI designs. In this paper, we present the first routing algorithm in the literatur...
Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang