730 search results - page 37 / 146 » Faster dimension reduction |
ICCD
2002
IEEE
14 years 5 months ago
2002
IEEE
Power is considered to be the major limiter to the design of more faster and complex processors in the near future. In order to address this challenge, a combination of process, c...
ICCAD
2001
IEEE
14 years 5 months ago
2001
IEEE
- This paper presents a spectrally-weighted balanced truncation technique for RLC interconnects, a technique needed when the interconnect circuit parameters change as a result of v...
DFT
2007
IEEE
14 years 3 months ago
2007
IEEE
The paper discusses a novel approach for reduction of fault detection latency in a selfchecking sequential circuit. The Authors propose decomposing the finite state machine (FSM) ...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
In this work a method to improve the loopback test used in RF analog circuits is described. The approach is targeted to the SoC environment, being able to reuse system resources i...
ICDE
2002
IEEE
14 years 1 months ago
2002
IEEE
We consider the use of data reduction techniques for the problem of approximate query answering. We focus on applications for which accurate answers to selective queries are requi...