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ISCA
1996
IEEE
99views Hardware» more  ISCA 1996»
14 years 2 months ago
Performance Comparison of ILP Machines with Cycle Time Evaluation
Many studies have investigated performance improvement through exploiting instruction-level parallelism (ILP) with a particular architecture. Unfortunately, these studies indicate...
Tetsuya Hara, Hideki Ando, Chikako Nakanishi, Masa...
MICRO
2000
IEEE
176views Hardware» more  MICRO 2000»
13 years 9 months ago
An Advanced Optimizer for the IA-64 Architecture
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel M....
MICRO
2010
IEEE
130views Hardware» more  MICRO 2010»
13 years 7 months ago
Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
Minseon Ahn, Eun Jung Kim
PPOPP
2010
ACM
14 years 7 months ago
Structure-driven optimizations for amorphous data-parallel programs
Irregular algorithms are organized around pointer-based data structures such as graphs and trees, and they are ubiquitous in applications. Recent work by the Galois project has pr...
Mario Méndez-Lojo, Donald Nguyen, Dimitrios...
ISCA
2009
IEEE
136views Hardware» more  ISCA 2009»
14 years 4 months ago
ECMon: exposing cache events for monitoring
The advent of multicores has introduced new challenges for programmers to provide increased performance and software reliability. There has been significant interest in technique...
Vijay Nagarajan, Rajiv Gupta