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ICCD
2004
IEEE
113views Hardware» more  ICCD 2004»
14 years 4 months ago
Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems
Abstract - This paper describes a communicationcentric design methodology that addresses the fundamental challenges induced by the emergence of truly heterogeneous Systems-on-Chip ...
Radu Marculescu, Diana Marculescu, Larry T. Pilegg...
FDTC
2006
Springer
74views Cryptology» more  FDTC 2006»
13 years 11 months ago
Fault Attack Resistant Cryptographic Hardware with Uniform Error Detection
Traditional hardware error detection methods based on linear codes make assumptions about the typical or expected errors and faults and concentrate the detection power towards the ...
Konrad J. Kulikowski, Mark G. Karpovsky, Alexander...
ISCA
2011
IEEE
270views Hardware» more  ISCA 2011»
12 years 11 months ago
Sampling + DMR: practical and low-overhead permanent fault detection
With technology scaling, manufacture-time and in-field permanent faults are becoming a fundamental problem. Multi-core architectures with spares can tolerate them by detecting an...
Shuou Nomura, Matthew D. Sinclair, Chen-Han Ho, Ve...
DATE
2005
IEEE
128views Hardware» more  DATE 2005»
14 years 1 months ago
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected b...
Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Ca...
ICAC
2005
IEEE
14 years 1 months ago
Multi-resolution Abnormal Trace Detection Using Varied-length N-grams and Automata
Detection and diagnosis of faults in a large-scale distributed system is a formidable task. Interest in monitoring and using traces of user requests for fault detection has been o...
Guofei Jiang, Haifeng Chen, Cristian Ungureanu, Ke...