372 search results - page 5 / 75 » Fault Testing for Reversible Circuits |
96
Voted
DATE
2005
IEEE
15 years 8 months ago
2005
IEEE
We investigate a new fault ordering heuristic for test generation in full-scan circuits. The heuristic is referred to as the accidental detection index. It associates a value ADI ...
108
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ATS
2009
IEEE
15 years 9 months ago
2009
IEEE
—A method of testing for parametric faults of analog circuits based on a polynomial representation of fault-free function of the circuit is presented. The response of the circuit...
145
Voted
ICCAD
1991
IEEE
15 years 6 months ago
1991
IEEE
This paper presents an efficient algorithm for the generation of diagnostic test patterns which distinguish between two arbitrary single stuck-at faults. The algorithm is able to ...
131
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DSN
2005
IEEE
15 years 8 months ago
2005
IEEE
It is now widely accepted that the CMOS technology implementing irreversible logic will hit a scaling limit beyond 2016, and that the increased power dissipation is a major limiti...
133
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ASPDAC
2009
ACM
15 years 9 months ago
2009
ACM
Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologie...