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ICALT
2005
IEEE
14 years 1 months ago
ActiveTutor
In this paper we present an architecture dedicated to an intelligently assisted educational tool which integrates within a unified framework software rational agents both at the m...
Jean Pierre Fournier
ITC
1997
IEEE
73views Hardware» more  ITC 1997»
13 years 11 months ago
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has s...
Indradeep Ghosh, Niraj K. Jha, Sujit Dey
ICSEA
2006
IEEE
14 years 1 months ago
Testing a Network by Inferring Representative State Machines from Network Traces
— This paper describes an innovative approach to network testing based on automatically generating and analyzing state machine models of network behavior. The models are generate...
Nancy D. Griffeth, Yuri Cantor, Constantinos Djouv...
MICRO
2008
IEEE
159views Hardware» more  MICRO 2008»
14 years 1 months ago
A novel cache architecture with enhanced performance and security
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
Zhenghong Wang, Ruby B. Lee
IEEEPACT
2006
IEEE
14 years 1 months ago
Whole-program optimization of global variable layout
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...
Nathaniel McIntosh, Sandya Mannarswamy, Robert Hun...