47 search results - page 8 / 10 » Fault Tolerant System Design Method Based on Self-Checking C... |
DAC
2008
ACM
14 years 8 months ago
2008
ACM
As integrated circuit technology plumbs ever greater depths in the scaling of feature sizes, maintaining the paradigm of deterministic Boolean computation is increasingly challeng...
HPCA
2006
IEEE
14 years 7 months ago
2006
IEEE
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-...
ISPA
2004
Springer
14 years 23 days ago
2004
Springer
Static DHT topologies influence important features of such DHTs such as scalability, communication load balancing, routing efficiency and fault tolerance. Nevertheless, it is co...
LCTRTS
2010
Springer
14 years 5 days ago
2010
Springer
Continuous technology scaling has brought us to a point, where transistors have become extremely susceptible to cosmic radiation strikes, or soft errors. Inside the processor, cac...