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» Fault emulation: a new approach to fault grading
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ATS
2009
IEEE
111views Hardware» more  ATS 2009»
14 years 2 months ago
Dynamic Compaction in SAT-Based ATPG
SAT-based automatic test pattern generation has several advantages compared to conventional structural procedures, yet often yields too large test sets. We present a dynamic compa...
Alejandro Czutro, Ilia Polian, Piet Engelke, Sudha...
VTS
2007
IEEE
100views Hardware» more  VTS 2007»
14 years 2 months ago
Using Scan-Dump Values to Improve Functional-Diagnosis Methodology
In this paper, we identify two main bottlenecks in the functional diagnosis flow and propose new ways to overcome these. Our approach completely eliminates the “Primary Input (P...
Vishnu C. Vimjam, Enamul Amyeen, Ruifeng Guo, Srik...
DFT
2005
IEEE
64views VLSI» more  DFT 2005»
14 years 1 months ago
Implementation of Concurrent Checking Circuits by Independent Sub-circuits
The present paper proposes a new method for detecting arbitrary faults in a functional circuit when the set of codewords is limited and known in advance. The method is based on im...
Vladimir Ostrovsky, Ilya Levin
ICCAD
1997
IEEE
134views Hardware» more  ICCAD 1997»
14 years 5 days ago
Post-route optimization for improved yield using a rubber-band wiring model
This paper presents a unique approach to improve yield given a routed layout. Currently after routing has been completed and compacted, it generally proceeds to verification witho...
Jeffrey Z. Su, Wayne Wei-Ming Dai
DAC
1997
ACM
14 years 4 days ago
STARBIST: Scan Autocorrelated Random Pattern Generation
This paper presents a new scan-based BIST scheme which achieves very high fault coverage without the deficiencies of previously proposed schemes. This approach utilizes scan order...
Kun-Han Tsai, Sybille Hellebrand, Janusz Rajski, M...