327 search results - page 61 / 66 » Fault emulation: a new approach to fault grading |
DT
2000
13 years 7 months ago
2000
Effective high-level ATPG tools are increasingly needed, as an essential element in the quest for reducing as much as possible the designer work on gate-level descriptions. We pro...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
CAV
2009
Springer
14 years 8 months ago
2009
Springer
ity Abstraction for Declarative Networking Applications Juan A. Navarro P?erez, Andrey Rybalchenko, and Atul Singh Max Planck Institute for Software Systems (MPI-SWS) Declarative N...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Several recent processor designs have proposed to enhance performance by increasing the clock frequency to the point where timing faults occur, and by adding error-correcting supp...
WCW
2004
Springer
14 years 1 months ago
2004
Springer
Internet overlay services must adapt to the substrate network topology and link properties to achieve high performance. A common overlay structure management layer is desirable fo...