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» Fault simulation on reconfigurable hardware
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ARC
2010
Springer
183views Hardware» more  ARC 2010»
13 years 9 months ago
Integrated Design Environment for Reconfigurable HPC
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time spent, not for developing efficient FPGA code but fo...
Lilian Janin, Shoujie Li, Doug Edwards
ITC
1995
IEEE
122views Hardware» more  ITC 1995»
14 years 21 days ago
A Fault Model and a Test Method for Analog Fuzzy Logic Circuits
A nalog circuit implementations of fuzzy logic are characterized by performing logical connectives of analog signals. They can be considered as generalization of digital circuits ...
Stefan Weiner
DATE
2003
IEEE
189views Hardware» more  DATE 2003»
14 years 2 months ago
Energy-Aware Adaptive Checkpointing in Embedded Real-Time Systems
We present an integrated approach that provides fault tolerance and dynamic power management for a real-time task executing in an embedded system. Fault tolerance is achieved thro...
Ying Zhang, Krishnendu Chakrabarty
VTS
2002
IEEE
120views Hardware» more  VTS 2002»
14 years 2 months ago
Test Pattern Generation for Signal Integrity Faults on Long Interconnects
In this paper, we present a test pattern generation algorithm aiming at signal integrity faults on long interconnects. This is achieved by considering the effect of inputs and par...
Amir Attarha, Mehrdad Nourani
VTS
2003
IEEE
127views Hardware» more  VTS 2003»
14 years 2 months ago
Bist Reseeding with very few Seeds
Reseeding is used to improve fault coverage of pseudorandom testing. The seed corresponds to the initial state of the LFSR before filling the scan chain. The number of determinist...
Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McC...