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» Fault simulation on reconfigurable hardware
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VTS
2003
IEEE
131views Hardware» more  VTS 2003»
14 years 2 months ago
Efficient Implication - Based Untestable Bridge Fault Identifier
: This paper presents a novel, low cost technique based on implications to identify untestable bridging faults in sequential circuits. Sequential symbolic simulation [1] is first p...
Manan Syal, Michael S. Hsiao, Kiran B. Doreswamy, ...
DATE
2010
IEEE
161views Hardware» more  DATE 2010»
14 years 2 months ago
Aging-resilient design of pipelined architectures using novel detection and correction circuits
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...
Hamed F. Dadgour, Kaustav Banerjee
ET
2007
101views more  ET 2007»
13 years 9 months ago
Towards Nanoelectronics Processor Architectures
In this paper, we focus on reliability, one of the most fundamental and important challenges, in the nanoelectronics environment. For a processor architecture based on the unreliab...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
ISSTA
2009
ACM
14 years 3 months ago
Specifying the worst case: orthogonal modeling of hardware errors
During testing, the execution of valid cases is only one part of the task. Checking the behavior in boundary situations and in the presence of errors is an equally important subje...
Jewgenij Botaschanjan, Benjamin Hummel
DSD
2006
IEEE
135views Hardware» more  DSD 2006»
14 years 25 days ago
Hardware-Software Codesign of a Vector Co-processor for Public Key Cryptography
Until now, most cryptography implementations on parallel architectures have focused on adapting the software to SIMD architectures initially meant for media applications. In this ...
Jacques J. A. Fournier, Simon W. Moore