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» Fault simulation on reconfigurable hardware
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ITC
1991
IEEE
86views Hardware» more  ITC 1991»
14 years 20 days ago
Test Pattern Generation for Realistic Bridge Faults in CMOS ICs
Two approaches have been used to balance the cost of generating e ective tests for ICs and the need to increase the ICs' quality level. The rst approach favorsusing high-leve...
F. Joel Ferguson, Tracy Larrabee
ISCA
2012
IEEE
224views Hardware» more  ISCA 2012»
11 years 11 months ago
A first-order mechanistic model for architectural vulnerability factor
Soft error reliability has become a first-order design criterion for modern microprocessors. Architectural Vulnerability Factor (AVF) modeling is often used to capture the probab...
Arun A. Nair, Stijn Eyerman, Lieven Eeckhout, Lizy...
ICCD
2004
IEEE
134views Hardware» more  ICCD 2004»
14 years 6 months ago
An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks
— We propose an automatic test pattern generation (ATPG) framework for combinational threshold networks. The motivation behind this work lies in the fact that many emerging nanot...
Pallav Gupta, Rui Zhang, Niraj K. Jha
ITC
2003
IEEE
127views Hardware» more  ITC 2003»
14 years 2 months ago
Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects
In this paper, we study the possibility of using logic defect-level prediction models to predict the detection behavior of statistical timing defects. We compare two known logic m...
Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting...
ICCAD
1995
IEEE
180views Hardware» more  ICCAD 1995»
14 years 22 days ago
Design based analog testing by Characteristic Observation Inference
In this paper, a new approach to analog test design based on the circuit design process, called Characteristic Observation Inference (COI), is presented. In many situations, it is...
Walter M. Lindermeir, Helmut E. Graeb, Kurt Antrei...