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» Fault simulation on reconfigurable hardware
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ISCA
2006
IEEE
154views Hardware» more  ISCA 2006»
14 years 3 months ago
An Integrated Framework for Dependable and Revivable Architectures Using Multicore Processors
This paper presents a high-availability system architecture called INDRA — an INtegrated framework for Dependable and Revivable Architecture that enhances a multicore processor ...
Weidong Shi, Hsien-Hsin S. Lee, Laura Falk, Mrinmo...
FPGA
2006
ACM
195views FPGA» more  FPGA 2006»
14 years 24 days ago
An adaptive Reed-Solomon errors-and-erasures decoder
The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful def...
Lilian Atieno, Jonathan Allen, Dennis Goeckel, Rus...
DATE
2008
IEEE
110views Hardware» more  DATE 2008»
14 years 3 months ago
Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set
One of the upcoming challenges in embedded processing is to incorporate an increasing amount of adaptivity in order to respond to the multifarious constraints induced by today’s...
Lars Bauer, Muhammad Shafique, Stephanie Kreutz, J...
ERSA
2004
129views Hardware» more  ERSA 2004»
13 years 10 months ago
A Methodology for Energy Efficient Application Synthesis Using Platform FPGAs
Platform FPGAs incorporate many different components, such as processor core(s), reconfigurable logic, memory, etc., onto a single chip. When an application is synthesized on platf...
Jingzhao Ou, Viktor K. Prasanna
DATE
2006
IEEE
66views Hardware» more  DATE 2006»
14 years 3 months ago
On test conditions for the detection of open defects
The impact of test conditions on the detectability of open defects is investigated. We performed an inductive fault analysis on representative standard gates. The simulation resul...
Bram Kruseman, Manuel Heiligers