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HPCA
2009
IEEE
14 years 8 months ago
Accurate microarchitecture-level fault modeling for studying hardware faults
Decreasing hardware reliability is expected to impede the exploitation of increasing integration projected by Moore's Law. There is much ongoing research on efficient fault t...
Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu...
CGO
2005
IEEE
14 years 1 months ago
SWIFT: Software Implemented Fault Tolerance
To improve performance and reduce power, processor designers employ advances that shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates. Howev...
George A. Reis, Jonathan Chang, Neil Vachharajani,...
ICDCSW
2008
IEEE
14 years 2 months ago
Automated Addition of Fault-Tolerance to SCR Toolset: A Case Study
Automated addition of fault-tolerance to existing programs is highly desirable, as it allows the designer to focus on the system behavior in the absence of faults and leave the fa...
Fuad Abujarad, Sandeep S. Kulkarni
DATE
2008
IEEE
182views Hardware» more  DATE 2008»
14 years 2 months ago
A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking
— As the feature size of transistors gets smaller, fabricating them becomes challenging. Manufacturing process follows various corrective design-for-manufacturing (DFM) steps to ...
Swaroop Ghosh, Patrick Ndai, Kaushik Roy
CODES
2010
IEEE
13 years 4 months ago
Hardware/software optimization of error detection implementation for real-time embedded systems
This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant realtime distributed embedded systems used for safe...
Adrian Lifa, Petru Eles, Zebo Peng, Viacheslav Izo...