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ISLPED
2007
ACM
92views Hardware» more  ISLPED 2007»
13 years 9 months ago
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI
Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) ...
Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh
MPC
2010
Springer
152views Mathematics» more  MPC 2010»
14 years 13 days ago
Lucy-n: a n-Synchronous Extension of Lustre
Synchronous functional languages such as Lustre or Lucid Synchrone define a restricted class of Kahn Process Networks which can be executed with no buffer. Every expression is as...
Louis Mandel, Florence Plateau, Marc Pouzet
SWAT
1994
Springer
94views Algorithms» more  SWAT 1994»
13 years 11 months ago
On Self-Stabilizing Wait-Free Clock Synchronization
Protocols which can tolerate any number of processors failing by ceasing operation for an unbounded number of steps and resuming operation (with or) without knowing that they were...
Marina Papatriantafilou, Philippas Tsigas
ASYNC
2002
IEEE
150views Hardware» more  ASYNC 2002»
14 years 19 days ago
Clock Synchronization through Handshake Signalling
We present a method for synchronizing pausible clocks in GALS (Globally Asynchronous, Locally Synchronous) systems. In contrast to most conventional GALS schemes the method is not...
Joep L. W. Kessels, Suk-Jin Kim, Ad M. G. Peeters,...
APLAS
2008
ACM
13 years 9 months ago
Abstraction of Clocks in Synchronous Data-Flow Systems
ion of Clocks in Synchronous Data-flow Systems Albert Cohen1 , Louis Mandel2 , Florence Plateau2 , and Marc Pouzet23 1 INRIA Saclay - Ile-de-France, Orsay, France 2 LRI, Univ. Pari...
Albert Cohen, Louis Mandel, Florence Plateau, Marc...