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ISLPED
2003
ACM
85views Hardware» more  ISLPED 2003»
14 years 28 days ago
Energy recovery clocking scheme and flip-flops for ultra low-energy applications
A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power clocking schemes would be promising approaches for futu...
Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy
ENTCS
2008
110views more  ENTCS 2008»
13 years 7 months ago
Performance Evaluation of Elastic GALS Interfaces and Network Fabric
This paper reports on the design of a test chip built to test a) a new latency insensitive network fabric protocol and circuits, b) a new synchronizer design, and c) how efficient...
JunBok You, Yang Xu, Hosuk Han, Kenneth S. Stevens
ASYNC
2006
IEEE
72views Hardware» more  ASYNC 2006»
14 years 1 months ago
Measuring Deep Metastability
Present measurement techniques do not allow synchronizer reliability to be measured in the region of most interest, that is, beyond the first half cycle of the synchronizer clock....
David Kinniment, Keith Heron, Gordon Russell
DAC
1994
ACM
13 years 11 months ago
Clock Grouping: A Low Cost DFT Methodology for Delay Testing
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault co...
Wen-Chang Fang, Sandeep K. Gupta
PODC
1996
ACM
13 years 12 months ago
Fail-Awareness in Timed Asynchronous Systems
We address the problem of the impossibility of implementing synchronous fault-tolerant service specifications in asynchronous distributed systems. We introduce a method for weaken...
Christof Fetzer, Flaviu Cristian