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HPCA
2006
IEEE
14 years 8 months ago
Dynamic power-performance adaptation of parallel computation on chip multiprocessors
Previous proposals for power-aware thread-level parallelism on chip multiprocessors (CMPs) mostly focus on multiprogrammed workloads. Nonetheless, parallel computation of a single...
Jian Li, José F. Martínez
IPPS
1999
IEEE
14 years 4 days ago
Dynamically Scheduling the Trace Produced During Program Execution into VLIW Instructions
VLIW machines possibly provide the most direct way to exploit instruction level parallelism; however, they cannot be used to emulate current general-purpose instruction set archit...
Alberto Ferreira de Souza, Peter Rounce
ISCAPDCS
2004
13 years 9 months ago
An Adaptive OpenMP Loop Scheduler for Hyperthreaded SMPs
Hyperthreaded(HT) and simultaneous multithreaded (SMT) processors are now available in commodity workstations and servers. This technology is designed to increase throughput by ex...
Yun Zhang, Mihai Burcea, Victor Cheng, Ron Ho, Mic...
EUROPAR
2009
Springer
14 years 15 days ago
A New Genetic Algorithm for Scheduling for Large Communication Delays
Abstract. In modern parallel and distributed systems, the time for exchanging data is usually larger than that for computing elementary operations. Consequently, these communicatio...
Johnatan E. Pecero, Denis Trystram, Albert Y. Zoma...
28
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IPPS
2000
IEEE
14 years 7 days ago
A General Parallel Simulated Annealing Library and its Application in Airline Industry
To solve real-world discrete optimization problems approximately metaheuristics such as simulated annealing and other local search methods are commonly used. For large instances o...
Georg Kliewer, Stefan Tschöke