Dynamic power-performance adaptation of parallel computation on chip multiprocessors

Previous proposals for power-aware thread-level parallelism on chip multiprocessors (CMPs) mostly focus on multiprogrammed workloads. Nonetheless, parallel computation of a single application is critical in light of the expanding performance demands of important future workloads. This work addresses the problem of dynamically optimizing power consumption of a parallel application that executes on a many-core CMP under a given performance constraint. The optimization space is twodimensional, allowing changes in the number of active processors and applying dynamic voltage/frequency scaling. We demonstrate that the particular optimum operating point depends nontrivially on the power-performance characteristics of the CMP, the application's behavior, and the particular performance target. We present simple, low-overhead heuristics for dynamic optimization that significantly cut down on the search effort along both dimensions of the optimization space. In our evaluation of several par...

• Type: Conference
• Year: 2006
• Where: HPCA
• Authors: Jian Li, José F. Martínez
• Keywords: Computer Architecture, HPCA 2006, Important Future Workloads, Low-overhead Heuristics, Particular Performance Target