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HPCA
2004
IEEE
14 years 8 months ago
2004
IEEE
This paper focuses on generating efficient software pipelined schedules for in-order machines, which we call Converged Trace Schedules. For a candidate loop, we form a string of t...
IPPS
1998
IEEE
14 years 7 days ago
1998
IEEE
Abstract. The nano-threads programming model was proposed to effectively integrate multiprogramming on shared-memory multiprocessors, with the exploitation of fine-grain parallelis...
ASPDAC
1998
ACM
14 years 7 days ago
1998
ACM
— The paper introduces a novel co-compiler and its “vertical” parallelization method, including a general model for co-operating host/accelerator platforms and a new parallel...
ISCA
2008
IEEE
14 years 2 months ago
2008
IEEE
Efficiently utilizing off-chip DRAM bandwidth is a critical issue in designing cost-effective, high-performance chip multiprocessors (CMPs). Conventional memory controllers deli...
IJPP
2010
13 years 5 months ago
2010
Exploiting the full computational power of current hierarchical multiprocessor machines requires a very careful distribution of threads and data among the underlying non-uniform ar...