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» Fault-Tolerant Resource Reasoning
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2009
ACM
14 years 4 months ago
Flexible cache error protection using an ECC FIFO
We present ECC FIFO, a mechanism enabling two-tiered last-level cache error protection using an arbitrarily strong tier-2 code without increasing on-chip storage. Instead of addin...
Doe Hyun Yoon, Mattan Erez
FPGA
2010
ACM
191views FPGA» more  FPGA 2010»
14 years 4 months ago
Voter insertion algorithms for FPGA designs using triple modular redundancy
Triple Modular Redundancy (TMR) is a common reliability technique for mitigating single event upsets (SEUs) in FPGA designs operating in radiation environments. For FPGA systems t...
Jonathan M. Johnson, Michael J. Wirthlin
CODES
2008
IEEE
14 years 4 months ago
Symbolic voter placement for dependability-aware system synthesis
This paper presents a system synthesis approach for dependable embedded systems. The proposed approach significantly extends previous work by automatically inserting fault detect...
Felix Reimann, Michael Glabeta, Martin Lukasiewycz...
ICDCS
2008
IEEE
14 years 4 months ago
stdchk: A Checkpoint Storage System for Desktop Grid Computing
— Checkpointing is an indispensable technique to provide fault tolerance for long-running high-throughput applications like those running on desktop grids. This paper argues that...
Samer Al-Kiswany, Matei Ripeanu, Sudharshan S. Vaz...
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
14 years 4 months ago
A low-SER efficient core processor architecture for future technologies
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...