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» Features of Future Network Processor Architectures
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IROS
2006
IEEE
112views Robotics» more  IROS 2006»
14 years 1 months ago
Requirements to UPnP for Robot Middleware
– The UPnP (Universal Plug and Play) defines an architecture for pervasive peer-to-peer network connectivity of intelligent appliances. It shares the service oriented architectur...
Sang Chul Ahn, Jung-Woo Lee, Kiwoong Lim, Heedong ...
CODES
2006
IEEE
13 years 11 months ago
Automatic phase detection for stochastic on-chip traffic generation
During System on Chip (SoC) design, Network on Chip (NoC) prototyping is used for adapting NoC parameters to the application running on the chip. This prototyping is currently don...
Antoine Scherrer, Antoine Fraboulet, Tanguy Risset
HPDC
2009
IEEE
14 years 2 months ago
Maintaining reference graphs of globally accessible objects in fully decentralized distributed systems
Since the advent of electronic computing, the processors’ clock speed has risen tremendously. Now that energy efficiency requirements have stopped that trend, the number of proc...
Björn Saballus, Thomas Fuhrmann
MICRO
2008
IEEE
119views Hardware» more  MICRO 2008»
14 years 2 months ago
The StageNet fabric for constructing resilient multicore systems
Scaling of CMOS feature size has long been a source of dramatic performance gains. However, the reduction in voltage levels has not been able to match this rate of scaling, leadin...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason ...
FPL
2010
Springer
146views Hardware» more  FPL 2010»
13 years 5 months ago
Software Managed Distributed Memories in MPPAs
When utilizing reconfigurable hardware there are many applications that will require more memory than is available in a single hardware block. While FPGAs have tools and mechanisms...
Robin Panda, Jimmy Xu, Scott Hauck