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» Features of Future Network Processor Architectures
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MICRO
2006
IEEE
155views Hardware» more  MICRO 2006»
14 years 1 months ago
In-Network Cache Coherence
With the trend towards increasing number of processor cores in future chip architectures, scalable directory-based protocols for maintaining cache coherence will be needed. Howeve...
Noel Eisley, Li-Shiuan Peh, Li Shang
HOTI
2008
IEEE
14 years 2 months ago
Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics
We present a new monolithic silicon photonics technology suited for integration with standard bulk CMOS processes, which reduces costs and improves opto-electrical coupling compar...
Christopher Batten, Ajay Joshi, Jason Orcutt, Anat...
ISPASS
2007
IEEE
14 years 1 months ago
PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator
In this paper, we introduce PTLsim, a cycle accurate full system x86-64 microprocessor simulator and virtual machine. PTLsim models a modern superscalar out of order x86-64 proces...
Matt T. Yourst
TRIDENTCOM
2010
IEEE
13 years 5 months ago
Interoperability of Lightpath Provisioning Systems in a Multi-domain Testbed
On-demand services are a key feature of Future Internet architectures. Already today research networks around the world provide dedicated optical circuits (lightpaths) to scientist...
Alfred Wan, Paola Grosso, Cees de Laat
ICCD
2003
IEEE
111views Hardware» more  ICCD 2003»
14 years 4 months ago
Routed Inter-ALU Networks for ILP Scalability and Performance
Modern processors rely heavily on broadcast networks to bypass instruction results to dependent instructions in the pipeline. However, as clock rates increase, architectures get w...
Karthikeyan Sankaralingam, Vincent Ajay Singh, Ste...