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FPL
2008
Springer
117views Hardware» more  FPL 2008»
13 years 9 months ago
A versatile hardware architecture for a CFAR detector based on a linear insertion sorter
This paper presents a versatile hardware architecture that implements six variant of the CFAR detector based on linear and non-linear operations. Since some implemented CFAR detec...
Roberto Perez-Andrade, René Cumplido, Claud...
DELTA
2008
IEEE
14 years 1 months ago
A Visual Notation for Processor and Resource Scheduling
Scheduling of concurrent processors in a real-time image processing system on FPGA (Field programmable gate array) hardware is a not a trivial task. We propose a number of graphic...
Christopher T. Johnston, Paul J. Lyons, Donald G. ...
DATE
2005
IEEE
115views Hardware» more  DATE 2005»
14 years 1 months ago
An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs
This paper presents an infrastructure to test the functionality of the specific architectures output by a highlevel compiler targeting dynamically reconfigurable hardware. It resu...
Rui Rodrigues, João M. P. Cardoso
EH
2003
IEEE
138views Hardware» more  EH 2003»
14 years 21 days ago
Implementing Evolution of FIR-Filters Efficiently in an FPGA
Reconfigurable hardware devices make it possible to change the topology of electronic circuits at runtime. Using reconfigurable devices as a platform for Evolvable hardware (EHW) ...
Knut Arne Vinger, Jim Torresen
CSREAESA
2006
13 years 8 months ago
In-House Built Bipedal Walking Robot
In this project, an in-house built bipedal walking Robot uses two direct current gear motors to power its legs. Each leg could bend at the knee to assist the walking routines. In ...
Kok-Swee Sim, Yee Kin Lum, Chih Ping Tso