172 search results - page 22 / 35 » FinFET-based SRAM design |
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
VLSID
2009
IEEE
14 years 8 months ago
2009
IEEE
We analyze the neutron induced soft error rate (SER). An induced error pulse is modeled by two parameters, probability of occurrence and probability density function of the pulse ...
ICC
2000
IEEE
13 years 12 months ago
2000
IEEE
Abstract—A major issue in router design for the next generation Internet is the fast IP address lookup mechanism. The existing scheme by Huang et al. performs the IP address look...
ASPLOS
2006
ACM
14 years 1 months ago
2006
ACM
While hardware instruction caches are present in virtually all general-purpose and high-performance microprocessors today, many embedded processors use SRAM or scratchpad memories...
ISLPED
2009
ACM
14 years 2 months ago
2009
ACM
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...