172 search results - page 28 / 35 » FinFET-based SRAM design |
ASPDAC
2004
ACM
14 years 27 days ago
2004
ACM
: A single-chip 512-point FFT processor is presented. This processor is based on the cached-memory architecture (CMA) with the resource-saving multidatapath radix-23 computation el...
GLOBECOM
2009
IEEE
13 years 11 months ago
2009
IEEE
Energy efficiency has become a critical concern in designing high speed packet classification engines for next generation routers. Although TCAM-based solutions can provide high th...
CASES
2009
ACM
13 years 10 months ago
2009
ACM
In this paper we introduce Resizable Data Composer-Cache (RDC-Cache). This novel cache architecture operates correctly at sub 500 mV in 65 nm technology tolerating large number of...
TC
1998
13 years 7 months ago
1998
—The very high levels of integration and submicron device sizes used in current and emerging VLSI technologies for FPGAs lead to higher occurrences of defects and operational fau...
RTAS
2010
IEEE
13 years 5 months ago
2010
IEEE
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...