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» Finding Hamilton Circuit in a Graph
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ASPDAC
2004
ACM
113views Hardware» more  ASPDAC 2004»
13 years 11 months ago
Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction
- Minimum area is one of the important objectives in technology mapping for lookup table-based FPGAs. It has been proven that the problem is NP-complete. This paper presents a poly...
Chi-Chou Kao, Yen-Tai Lai
DAC
2006
ACM
14 years 8 months ago
SAT sweeping with local observability don't-cares
SAT sweeping is a method for simplifying an AND/INVERTER graph (AIG) by systematically merging graph vertices from the inputs towards the outputs using a combination of structural...
Qi Zhu, Nathan Kitchen, Andreas Kuehlmann, Alberto...
TCAD
2008
97views more  TCAD 2008»
13 years 7 months ago
Encoding Large Asynchronous Controllers With ILP Techniques
State encoding is one of the most difficult problems in the synthesis of asynchronous controllers. This paper presents a method that can solve the problem of large controllers spec...
Josep Carmona, Jordi Cortadella
VISSYM
2007
13 years 9 months ago
Path Visualization for Adjacency Matrices
For displaying a dense graph, an adjacency matrix is superior than a node-link diagram because it is more compact and free of visual clutter. A node-link diagram, however, is far ...
Zeqian Shen, Kwan-Liu Ma
ASYNC
2001
IEEE
136views Hardware» more  ASYNC 2001»
13 years 11 months ago
Efficient Exact Two-Level Hazard-Free Logic Minimization
This paper presents a new approach to two-level hazardfree sum-of-products logic minimization. No currently available minimizers for single-output literal-exact two-level hazard-f...
Chris J. Myers, Hans M. Jacobson