The automated analysis of Feature Models (FMs) focuses on the usage of different logic paradigms and solvers to implement a number of analysis operations on FMs. The implementatio...
Sergio Segura, David Benavides, Antonio Ruiz Cort&...
This paper describes how the communication protocol of Mondex electronic purses can be specified and verified against desired security properties. The specification is developed by...
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
Saurabh K. Tiwary, Anubhav Gupta, Joel R. Phillips...
A verifying compiler is one that emits both object code and a proof of correspondence between object and source code.1 We report the use of ACL2 in building a verifying compiler f...
el Predicate Abstraction and Refinement Techniques for Verifying RTL Verilog Himanshu Jain, Daniel Kroening, Natasha Sharygina, and Edmund M. Clarke, Fellow, IEEE As a first step, ...
Himanshu Jain, Daniel Kroening, Natasha Sharygina,...