104 search results - page 5 / 21 » First-Class Synchronization Barriers |
MICRO
2006
IEEE
13 years 7 months ago
2006
IEEE
We examine the ability of CMPs, due to their lower onchip communication latencies, to exploit data parallelism at inner-loop granularities similar to that commonly targeted by vec...
ISCAS
2011
IEEE
12 years 11 months ago
2011
IEEE
Abstract— Multi-core processors are about to conquer embedded systems — it is not the question of whether they are coming but how the architectures of the microcontrollers shou...
SPAA
2012
ACM
11 years 10 months ago
2012
ACM
We present a highly-scalable non-blocking producer-consumer task pool, designed with a special emphasis on lightweight synchronization and data locality. The core building block o...
CASES
2007
ACM
13 years 11 months ago
2007
ACM
Many MPSoC applications are loop-intensive and amenable to automatic parallelization with suitable compiler support. One of the key components of any compiler-parallelized code is...
PPOPP
2005
ACM
14 years 1 months ago
2005
ACM
We want to perform compile-time analysis of an SPMD program and place barriers in it to synchronize it correctly, minimizing the runtime cost of the synchronization. This is the b...