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MICRO
1997
IEEE
90views Hardware» more  MICRO 1997»
14 years 1 months ago
ProfileMe: Hardware Support for Instruction-Level Profiling on Out-of-Order Processors
Profile data is valuable for identifying performance bottlenecks and guiding optimizations. Periodic sampling of a processor's performance monitoring hardware is an effective...
Jeffrey Dean, James E. Hicks, Carl A. Waldspurger,...
ASAP
2007
IEEE
123views Hardware» more  ASAP 2007»
13 years 11 months ago
Estimating Area Costs of Custom Instructions for FPGA-based Reconfigurable Processors
FPGA (Field Programmable Gate Array) based reconfigurable processor has been shown to meet the increasingly challenging performance targets and shorter time-to-market pressures. I...
Siew Kei Lam, Thambipillai Srikanthan
FPL
2008
Springer
86views Hardware» more  FPL 2008»
13 years 11 months ago
Instruction buffer mode for multi-context Dynamically Reconfigurable Processors
In multi-context Dynamically Reconfigurable Processor Array (DRPA), the required number of contexts is often increased by those with low resource usage. In order to execute such c...
Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Ha...
CATA
2004
13 years 11 months ago
The Instruction Execution Mechanism for Responsive Multithreaded Processor
This paper describes the instruction execution mechanism of Responsive Multithreaded (RMT) Processor for distributed real-time processing. The execution order of each thread is co...
Tstomu Itou, Nobuyuki Yamasaki
HPCA
2006
IEEE
14 years 10 months ago
Efficient instruction schedulers for SMT processors
We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently propos...
Joseph J. Sharkey, Dmitry V. Ponomarev