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PLDI
2006
ACM
14 years 3 months ago
Automatic instruction scheduler retargeting by reverse-engineering
In order to generate high-quality code for modern processors, a compiler must aggressively schedule instructions, maximizing resource utilization for execution efficiency. For a ...
Matthew J. Bridges, Neil Vachharajani, Guilherme O...
ASAP
2008
IEEE
118views Hardware» more  ASAP 2008»
14 years 4 months ago
Bit matrix multiplication in commodity processors
Registers in processors generally contain words or, with the addition of multimedia extensions, short vectors of subwords of bytes or 16-bit elements. In this paper, we view the c...
Yedidya Hilewitz, Cédric Lauradoux, Ruby B....
IJES
2008
102views more  IJES 2008»
13 years 10 months ago
Alternative application-specific processor architectures for fast arbitrary bit permutations
Block ciphers are used to encrypt data and provide data confidentiality. For interoperability reasons, it is desirable to support a variety of block ciphers efficiently. Of the bas...
Zhijie Jerry Shi, Xiao Yang, Ruby B. Lee
ISQED
2008
IEEE
119views Hardware» more  ISQED 2008»
14 years 4 months ago
Instruction Scheduling for Variation-Originated Variable Latencies
The advance in semiconductor technologies presents the serious problem of parameter variations. They affect threshold voltage of transistors and thus circuit delay also has variat...
Toshinori Sato, Shingo Watanabe
SAMOS
2010
Springer
13 years 8 months ago
Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator
—Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and verification. State-of-the-art simulators using just-in-ti...
Igor Böhm, Björn Franke, Nigel P. Topham