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DATE
2008
IEEE
114views Hardware» more  DATE 2008»
14 years 4 months ago
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
Sanghyun Park, Aviral Shrivastava, Yunheung Paek
ICCAD
2005
IEEE
141views Hardware» more  ICCAD 2005»
14 years 6 months ago
Architecture and compilation for data bandwidth improvement in configurable embedded processors
Many commercially available embedded processors are capable of extending their base instruction set for a specific domain of applications. While steady progress has been made in t...
Jason Cong, Guoling Han, Zhiru Zhang
ISCC
2009
IEEE
210views Communications» more  ISCC 2009»
14 years 4 months ago
Towards a Java bytecodes compiler for Nios II soft-core processor
Reconfigurable computing is one of the most recent research topics in computer science. The Altera™ Nios II soft-core processor can be included in a large set of reconfigurable ...
Willian dos Santos Lima, Renata Spolon Lobato, Ale...
CASES
2009
ACM
14 years 4 months ago
Hybrid multithreading for VLIW processors
Several multithreading techniques have been proposed to reduce resource underutilization in Very Long Instruction Word (VLIW) processors. Simultaneous MultiThreading (SMT) is a po...
Manoj Gupta, Fermín Sánchez, Josep L...
IEEEPACT
2006
IEEE
14 years 4 months ago
Adaptive reorder buffers for SMT processors
In SMT processors, the complex interplay between private and shared datapath resources needs to be considered in order to realize the full performance potential. In this paper, we...
Joseph J. Sharkey, Deniz Balkan, Dmitry Ponomarev