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FCCM
2007
IEEE
101views VLSI» more  FCCM 2007»
14 years 4 months ago
Mapping Real Time Operating System on Reconfigurable Instruction Cell Based Architectures
This paper presents the porting of an RTOS Micro C/OS-II on a novel reconfigurable instruction cell based architecture which fills the gap between DSP, FPGA and ASIC with high per...
Han Wei, Mark Muir, Ioannis Nousias, Tughrul Arsla...
DSD
2003
IEEE
106views Hardware» more  DSD 2003»
14 years 3 months ago
Analytical Bounds on the Threads in IXP1200 Network Processor
Increasing link speeds have placed enormous burden on the processing requirements and the processors are expected to carry out a variety of tasks. Network Processors (NP) [1] [2] ...
S. T. G. S. Ramakrishna, H. S. Jamadagni
ISCA
1989
IEEE
1033views Hardware» more  ISCA 1989»
14 years 2 months ago
Can Dataflow Subsume von Neumann Computing?
: We explore the question: “What can a von Neumann processor borrow from dataflow to make it more suitable for a multiprocessor?’’ Starting with a simple, “RISC-like” ins...
Rishiyur S. Nikhil
ICALT
2005
IEEE
14 years 3 months ago
The Effect of Interactivity on Web-Based Instruction Learners' Attitude, Satisfaction, and Performances
The Internet breaks the limitations of time and space and provides a flexible platform for learning. Learning is a two-way communication and interactivity is a process to enhance ...
Juei-ni Sun, Yu-chen Hsu
INFOVIS
1999
IEEE
14 years 2 months ago
Visualizing Application Behavior on Superscalar Processors
The advent of superscalar processors with out-of-order execution makes it increasingly difficult to determine how well an application is utilizing the processor and how to adapt t...
Chris Stolte, Robert Bosch, Pat Hanrahan, Mendel R...