1563 search results - page 70 / 313 » Flexible instruction processors |
ARITH
2007
IEEE
14 years 4 months ago
2007
IEEE
This paper describes a new basis for the implementation of a shifter functional unit. We present a design based on the inverse butterfly and butterfly datapath circuits that perfo...
ERSA
2009
13 years 7 months ago
2009
We present the architecture and programming model for MORA, a coarse-grained reconfigurable processor aimed at multimedia applications. The MORA architecure is a MIMD machine consi...
ICCD
2002
IEEE
14 years 6 months ago
2002
IEEE
We present a co-simulation environment for multiprocessor architectures, that is based on SystemC and allows a transparent integration of instruction set simulators (ISSs) within ...
SAC
2006
ACM
14 years 3 months ago
2006
ACM
Esterel is a concurrent synchronous language for developing reactive systems. As an alternative to the classical software and hardware synthesis paths, the reactive processing app...
ICCD
2004
IEEE
14 years 6 months ago
2004
IEEE
As the performance gap between processors and memory systems increases, the CPU spends more time stalled waiting for data from main memory. Critical long latency instructions, suc...