Sciweavers

1563 search results - page 72 / 313
» Flexible instruction processors
Sort
View
ISCA
1999
IEEE
88views Hardware» more  ISCA 1999»
14 years 3 months ago
A Scalable Front-End Architecture for Fast Instruction Delivery
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet ...
Glenn Reinman, Todd M. Austin, Brad Calder
CODES
2006
IEEE
14 years 2 months ago
Application specific forwarding network and instruction encoding for multi-pipe ASIPs
Small area and code size are two critical design issues in most of embedded system designs. In this paper, we tackle these issues by customizing forwarding networks and instructio...
Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswar...
CASES
2001
ACM
14 years 2 months ago
Application specific architectures: a recipe for fast, flexible and power efficient designs
The general purpose processor has long been the focus of intense optimization efforts that have resulted in an impressive doubling of performance every 18 months. However, recent ...
Christopher T. Weaver, Rajeev Krishna, Lisa Wu, To...
CC
2004
Springer
14 years 4 months ago
Using Multiple Memory Access Instructions for Reducing Code Size
An important issue in embedded systems design is the size of programs. As computing devices decrease in size, yet with more and more functions, better code size optimizations are i...
Neil Johnson, Alan Mycroft
DATE
2002
IEEE
137views Hardware» more  DATE 2002»
14 years 4 months ago
Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models
The design of application (-domain) specific instructionset processors (ASIPs), optimized for code size, has traditionally been accompanied by the necessity to program assembly, ...
Qin Zhao, Bart Mesman, Twan Basten