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» Floating Point Unit Generation and Evaluation for FPGAs
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ARC
2010
Springer
188views Hardware» more  ARC 2010»
14 years 5 months ago
A Fused Hybrid Floating-Point and Fixed-Point Dot-Product for FPGAs
Dot-products are one of the essential and recurrent building blocks in scientific computing, and often take-up a large proportion of the scientific acceleration circuitry. The ac...
Antonio Roldao Lopes, George A. Constantinides
TVLSI
2008
149views more  TVLSI 2008»
13 years 10 months ago
Architectural Modifications to Enhance the Floating-Point Performance of FPGAs
With the density of FPGAs steadily increasing, FPGAs have reached the point where they are capable of implementing complex floating-point applications. However, their general-purpo...
Michael J. Beauchamp, Scott Hauck, Keith D. Underw...
ERSA
2006
129views Hardware» more  ERSA 2006»
14 years 7 days ago
Group-Alignment based Accurate Floating-Point Summation on FPGAs
Floating-point summation is one of the most important operations in scientific/numerical computing applications and also a basic subroutine (SUM) in BLAS (Basic Linear Algebra Sub...
Chuan He, Guan Qin, Mi Lu, Wei Zhao
FPL
2008
Springer
98views Hardware» more  FPL 2008»
14 years 12 days ago
Rapid estimation of power consumption for hybrid FPGAs
A hybrid FPGA consists of island-style fine-grained units and domain-specific coarse-grained units. This paper describes an approach to estimate the power consumption of a set of ...
Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Ste...
ARITH
2007
IEEE
14 years 5 months ago
P6 Binary Floating-Point Unit
The floating point unit of the next generation PowerPC is detailed. It has been tested at over 5 GHz. The design supports an extremely aggressive cycle time of 13 FO4 using a tech...
Son Dao Trong, Martin S. Schmookler, Eric M. Schwa...