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» Floorplan area minimization using Lagrangian relaxation
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ORL
2011
13 years 2 months ago
Convex approximations to sparse PCA via Lagrangian duality
We derive a convex relaxation for cardinality constrained Principal Component Analysis (PCA) by using a simple representation of the L1 unit ball and standard Lagrangian duality. ...
Ronny Luss, Marc Teboulle
ICCAD
2003
IEEE
219views Hardware» more  ICCAD 2003»
14 years 4 months ago
A Min-Cost Flow Based Detailed Router for FPGAs
Routing for FPGAs has been a very challenging problem due to the limitation of routing resources. Although the FPGA routing problem has been researched extensively, most algorithm...
Seokjin Lee, Yongseok Cheon, Martin D. F. Wong
FPGA
1995
ACM
93views FPGA» more  FPGA 1995»
13 years 11 months ago
Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping
In this paper, we present an improvement of the FlowMap algorithm, named CutMap, which combines depth and area minimization in the mapping process by computing min-cost min-height...
Jason Cong, Yean-Yow Hwang
ISPD
1998
ACM
101views Hardware» more  ISPD 1998»
13 years 11 months ago
Greedy wire-sizing is linear time
—The greedy wire-sizing algorithm (GWSA) has been experimentally shown to be very efficient, but no mathematical analysis on its convergence rate has ever been reported. In this...
Chris C. N. Chu, D. F. Wong
VLSID
2002
IEEE
120views VLSI» more  VLSID 2002»
14 years 8 months ago
Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing
We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according to a prescribed buffer site map. Specifically, we describe a provably good mult...
Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoi...