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» Flow Time Minimization under Energy Constraints
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DATE
2008
IEEE
66views Hardware» more  DATE 2008»
14 years 2 months ago
Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects
This paper presents a wrapper and TAM co-optimization method for reuse of SoC functional interconnects to minimize test time under area constraint. The proposed method consists of...
Tomokazu Yoneda, Hideo Fujiwara
ISVLSI
2006
IEEE
82views VLSI» more  ISVLSI 2006»
14 years 1 months ago
Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors
One major issue in designing image processors is to design a memory system that supports parallel access with a simple interconnection network. This paper presents a design method...
Masanori Hariyama, Michitaka Kameyama, Yasuhiro Ko...
VTS
2000
IEEE
126views Hardware» more  VTS 2000»
14 years 2 days ago
Static Compaction Techniques to Control Scan Vector Power Dissipation
Excessive switching activity during scan testing can cause average power dissipation and peak power during test to be much higher than during normal operation. This can cause prob...
Ranganathan Sankaralingam, Rama Rao Oruganti, Nur ...
CVPR
2010
IEEE
13 years 9 months ago
Simultaneous Searching of Globally Optimal Interacting Surfaces with Shape Priors
Multiple surface searching with only image intensity information is a difficult job in the presence of high noise and weak edges. We present in this paper a novel method for global...
Qi Song, Xiaodong Wu, Yunlong Liu, Mona Garvin, Mi...
AAAI
2007
13 years 10 months ago
Nonmyopic Informative Path Planning in Spatio-Temporal Models
In many sensing applications we must continuously gather information to provide a good estimate of the state of the environment at every point in time. A robot may tour an environ...
Alexandra Meliou, Andreas Krause, Carlos Guestrin,...