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» Forensic engineering techniques for VLSI CAD tools
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FCCM
2000
IEEE
144views VLSI» more  FCCM 2000»
14 years 10 days ago
Automatic Synthesis of Data Storage and Control Structures for FPGA-Based Computing Engines
Mapping computations written in high-level programming languages to FPGA-based computing engines requires programmers to generate the datapath responsible for the core of the comp...
Pedro C. Diniz, Joonseok Park
GLVLSI
2005
IEEE
85views VLSI» more  GLVLSI 2005»
14 years 1 months ago
Utilizing don't care states in SAT-based bounded sequential problems
Boolean Satisfiability (SAT) solvers are popular engines used throughout the verification world. Bounded sequential problems such as bounded model checking and bounded sequentia...
Sean Safarpour, Görschwin Fey, Andreas G. Ven...
GLVLSI
2003
IEEE
177views VLSI» more  GLVLSI 2003»
14 years 1 months ago
Congestion reduction in traditional and new routing architectures
In dense integrated circuit designs, management of routing congestion is essential; an over congested design may be unroutable. Many factors influence congestion: placement, rout...
Ameya R. Agnihotri, Patrick H. Madden
VIS
2004
IEEE
227views Visualization» more  VIS 2004»
14 years 9 months ago
Intuitive and Interactive Modification of Large Finite Element Models
Virtual prototyping is increasingly replacing real mock-ups and experiments in industrial product development. Part of this process is the simulation of structural and functional ...
Dirc Rose, Katrin Bidmon, Thomas Ertl
ISVLSI
2006
IEEE
89views VLSI» more  ISVLSI 2006»
14 years 1 months ago
System Exploration of SystemC Designs
Due to increasing design complexity new methodologies for system modeling have been established in VLSI CAD. The SystemC methodology gains a significant reduction of design cycle...
Christian Genz, Rolf Drechsler