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DATE
2004
IEEE
134views Hardware» more  DATE 2004»
15 years 8 months ago
Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor
ASIC designs for future communication applications cannot be simulated exhaustively. Formal Property Checking is a powerful technology to overcome the limitations of current funct...
Klaus Winkelmann, Hans-Joachim Trylus, Dominik Sto...
TYPES
2000
Springer
15 years 8 months ago
Executing Higher Order Logic
We report on the design of a prototyping component for the theorem prover Isabelle/HOL. Specifications consisting of datatypes, recursive functions and inductive definitions are co...
Stefan Berghofer, Tobias Nipkow
ROOM
2000
15 years 6 months ago
Structured Axiomatic Semantics for UML Models
In this paper we provide a systematic formal interpretation for most elements of the UML notation. This interpretation, in a structured temporal logic, enables precise analysis of...
Kevin Lano, Juan Bicarregui, Andy Evans
AICOM
2010
129views more  AICOM 2010»
15 years 4 months ago
Automated theorem proving in quasigroup and loop theory
We survey all known results in the area of quasigroup and loop theory to have been obtained with the assistance of automated theorem provers. We provide both informal and formal d...
J. D. Phillips, David Stanovský
IPL
2002
86views more  IPL 2002»
15 years 4 months ago
A semantics of sequence diagrams
We develop a formal semantics of sequence diagrams. The semantics is given in terms of our new temporal logic, named HDTL, which is designed to specify dynamically evolving system...
Seung Mo Cho, Hyung-Ho Kim, Sung Deok Cha, Doo-Hwa...