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» Formal Methods for Networks on Chips
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ASPDAC
2009
ACM
108views Hardware» more  ASPDAC 2009»
14 years 4 months ago
Synthesis of networks on chips for 3D systems on chips
Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (N...
Srinivasan Murali, Ciprian Seiculescu, Luca Benini...
DATE
2008
IEEE
170views Hardware» more  DATE 2008»
14 years 4 months ago
ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis
In this paper, we present a novel simulation approach for power grid network analysis. The new approach, called ETBR for extended truncated balanced realization, is based on model...
Duo Li, Sheldon X.-D. Tan, Bruce McGaughy
ASPDAC
2006
ACM
94views Hardware» more  ASPDAC 2006»
14 years 3 months ago
Mapping and configuration methods for multi-use-case networks on chips
Srinivasan Murali, Martijn Coenen, Andrei Radulesc...
DAC
2006
ACM
14 years 3 months ago
DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip
A novel routing algorithm, namely dynamic XY (DyXY) routing, is proposed for NoCs to provide adaptive routing and ensure deadlock-free and livelock-free routing at the same time. ...
Ming Li, Qing-An Zeng, Wen-Ben Jone
CAV
2009
Springer
156views Hardware» more  CAV 2009»
14 years 4 months ago
Towards Performance Prediction of Compositional Models in Industrial GALS Designs
Systems and Networks on Chips (NoCs) are a prime design focus of many hardware manufacturers. In addition to functional verification, which is a difficult necessity, the chip desi...
Nicolas Coste, Holger Hermanns, Etienne Lantreibec...