478 search results - page 66 / 96 » Formal Methods for Specifying, Validating, and Verifying Req... |
TKDE
2012
11 years 11 months ago
2012
— This paper presents a method for identifying a set of dense subgraphs of a given sparse graph. Within the main applications of this “dense subgraph problem”, the dense subg...
FAABS
2000
Springer
14 years 7 days ago
2000
Springer
To ful ll the needs of its deep space exploration program, NASAis actively supporting research and development in autonomy software. However, the reliable and cost-e ective develop...
MICRO
2008
IEEE
13 years 8 months ago
2008
IEEE
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to ...
VLSID
2001
IEEE
14 years 9 months ago
2001
IEEE
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
MEMOCODE
2007
IEEE
14 years 2 months ago
2007
IEEE
The always increasing complexity of digital system is overcome in design flows based on Transaction Level Modeling (TLM) by designing and verifying the system at difbstraction le...