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» Formal Models for Embedded System Design
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CODES
2007
IEEE
13 years 12 months ago
Synchronization after design refinements with sensitive delay elements
The synchronous computational model with its simple computation and communication mechanism makes it easy to describe, simulate and formally verify synchronous embedded systems at...
Tarvo Raudvere, Ingo Sander, Axel Jantsch
FDL
2008
IEEE
13 years 9 months ago
Scenario-based Validation of Embedded Systems
This paper describes a scenario-based methodology em-level design validation based on the Abstract State Machines formal method. This scenario-based approach complements an existi...
Angelo Gargantini, Elvinia Riccobene, Patrizia Sca...
FDL
2004
IEEE
13 years 11 months ago
UML System-Level Analysis and Design of Secure Communication Schemes for Embedded Systems
In this work we develop a secure communication protocol in the context of a Remote Meter Reading (RMR) System. We first analyze existing standards in secure communication (e.g. IP...
Mauro Prevostini, Giuseppe Piscopo, I. Stefanini
EMSOFT
2010
Springer
13 years 5 months ago
Initiating a design pattern catalog for embedded network systems
In the domain of desktop software, design patterns have had a profound impact; they are applied ubiquitously across a broad range of applications. Patterns serve both to promulgat...
Sally K. Wahba, Jason O. Hallstrom, Neelam Soundar...
ASPDAC
2009
ACM
249views Hardware» more  ASPDAC 2009»
14 years 17 days ago
Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model
— This paper proposes the first automatic approach to simultaneously generate Cycle Accurate and Cycle Count Accurate transaction level bus models. Since TLM (Transaction Level M...
Chen Kang Lo, Ren-Song Tsay